FET and MOSFET Notes FE Sem 2 Semiconductor Physics | MU

The phone in your pocket contains billions of transistors, and almost all of them are MOSFETs. Field-effect transistors (FETs) control current with an electric field set by a gate voltage instead of a base current, so they draw almost no input current, are easy to make very small and consume little power. This module of the Semiconductor Physics elective covers FET types (JFET and MOSFET), their structure and operation, the MOSFET in detail including enhancement and depletion modes and the threshold voltage, and MOSFET applications, especially the MOSFET as a switch. It maps to course outcome CO5 (plot I-V characteristics and understand applications of FETs) and has the largest teaching time (6 hours) in the course.

Summary

Field-effect transistors: A FET is a three-terminal semiconductor device in which the current through a conducting channel between the source (S) and drain (D) is controlled by the electric field produced by a voltage applied to the gate (G). It is unipolar, since current is carried by majority carriers only (electrons in n-channel and holes in p-channel devices). It is voltage-controlled, unlike the BJT which is current-controlled. FET types: the junction FET (JFET), in which the gate is a reverse-biased p-n junction, and the metal-oxide-semiconductor FET (MOSFET, also called IGFET), in which the gate is insulated from the channel by a thin oxide; MOSFETs are of enhancement type (E-MOSFET) and depletion type (D-MOSFET). Each type exists in n-channel and p-channel forms. Advantages over BJTs: very high input impedance (about \(10^9\) Ω for JFET and \(10^{12}\) Ω or more for MOSFET), low noise, better thermal stability (no thermal runaway, since mobility falls with temperature), smaller size, simpler fabrication and very low power, which makes MOSFETs ideal for integrated circuits. Disadvantages: lower gain-bandwidth product than BJTs in some uses, and MOSFET gates are easily damaged by static charge.

JFET structure and operation: An n-channel JFET is a bar of n-type silicon with ohmic contacts at its ends, the source and drain. Two heavily doped p⁺ regions are diffused into opposite sides of the bar and connected together to form the gate. The n region between the gates is the channel. In operation the gate-source junction is always reverse biased (V_GS ≤ 0 for n-channel), so the gate current is practically zero. With V_GS = 0 and a small V_DS, electrons flow from source to drain through the channel, and the device acts like a resistor (ohmic region). As V_DS increases, the reverse bias is larger near the drain, so the depletion regions widen more at the drain end and the channel narrows there. At \(V_{DS} = |V_P|\) (with V_GS = 0) the depletion regions almost meet: the channel is pinched off, and the drain current saturates at its maximum value I_DSS. Beyond pinch-off, I_D stays nearly constant (saturation or constant-current region) until breakdown. If V_GS is made negative, the depletion regions are wider from the start, the channel is narrower, pinch-off occurs at a lower V_DS and the saturated current is smaller. At \(V_{GS} = V_P\) (the pinch-off or gate-source cut-off voltage, for example −4 V) the channel is closed completely and I_D = 0. In saturation the drain current follows Shockley's equation \(I_D = I_{DSS}\left(1 - \dfrac{V_{GS}}{V_P}\right)^2\). The transfer characteristic (I_D vs V_GS) is therefore a parabola from I_DSS at V_GS = 0 to zero at V_P. Transconductance \(g_m = \Delta I_D/\Delta V_{GS} = \dfrac{2I_{DSS}}{|V_P|}\left(1 - \dfrac{V_{GS}}{V_P}\right)\). A JFET is a depletion-mode device: it is normally ON and is turned off by gate voltage.

MOSFET structure: An n-channel MOSFET is built on a lightly doped p-type silicon substrate (body). Two heavily doped n⁺ regions are diffused into it to form the source and drain, separated by a distance called the channel length L. The surface between them is covered by a very thin layer of silicon dioxide (SiO2, the gate oxide, a few nanometres to tens of nanometres thick), and on top of the oxide lies the gate electrode (originally aluminium, then heavily doped polysilicon, and now metal with high-k dielectrics in advanced chips). Metal contacts connect the source, drain and gate; the substrate is usually connected to the source. The gate, oxide and semiconductor form a capacitor; since the oxide is an insulator, the gate current is essentially zero and the input resistance is extremely high. The name MOS describes this metal-oxide-semiconductor stack.

Enhancement mode (E-MOSFET): In an n-channel enhancement MOSFET there is no channel between source and drain at V_GS = 0: the path source-substrate-drain contains two back-to-back p-n junctions, so no current flows (normally OFF). When a positive V_GS is applied, the gate acts as one plate of a capacitor: holes in the p substrate under the gate are repelled, leaving negative acceptor ions (depletion layer), and minority electrons are attracted to the surface. When V_GS exceeds the threshold voltage V_T, the electron concentration at the surface exceeds the hole concentration in the bulk: a thin n-type inversion layer forms under the oxide and connects source to drain. This induced n-channel conducts, and the more V_GS exceeds V_T, the more electrons it contains, so the channel is enhanced by the gate voltage. Output characteristics (I_D vs V_DS for several V_GS > V_T): in the ohmic (linear or triode) region, for \(V_{DS} < V_{GS} - V_T\), the channel behaves as a voltage-controlled resistor, \(I_D = k_n\left[2(V_{GS} - V_T)V_{DS} - V_{DS}^2\right]\); when \(V_{DS} \geq V_{GS} - V_T\), the channel is pinched off at the drain end and the current saturates: \(I_D = k(V_{GS} - V_T)^2\). The transfer characteristic is a parabola starting at V_T. The p-channel E-MOSFET works the same way with an n substrate, p⁺ source and drain, and negative voltages.

Depletion mode (D-MOSFET): A depletion MOSFET has a channel built in during manufacture: a lightly doped n-type region diffused between the n⁺ source and drain under the oxide. At V_GS = 0 it already conducts a current I_DSS (normally ON). With negative V_GS, the gate repels electrons from the channel and induces positive charge, depleting the channel of carriers and reducing I_D (depletion mode), until at V_GS = V_P (or V_GS(off)) the channel is cut off. With positive V_GS, extra electrons are attracted into the channel, increasing I_D above I_DSS (enhancement mode). Since the gate is insulated, positive gate voltage causes no gate current, unlike a JFET. Its transfer characteristic follows the same Shockley equation \(I_D = I_{DSS}(1 - V_{GS}/V_P)^2\), extended to positive V_GS. Symbols: the D-MOSFET symbol shows a continuous channel line; the E-MOSFET symbol shows a broken (dashed) channel line, indicating no channel at zero gate voltage.

Threshold voltage: The threshold voltage V_T of an n-channel enhancement MOSFET is the minimum gate-source voltage at which a conducting inversion layer forms at the surface, defined as the gate voltage at which the surface potential reaches twice the Fermi potential of the substrate (\(\psi_s = 2\phi_F\), strong inversion). It is given by \(V_T = V_{FB} + 2\phi_F + \dfrac{\sqrt{2\varepsilon_se N_A(2\phi_F)}}{C_{ox}}\), where \(\phi_F = (kT/e)\ln(N_A/n_i)\) is the Fermi potential of the p substrate, \(C_{ox} = \varepsilon_{ox}/t_{ox}\) is the oxide capacitance per unit area, the last term is the voltage needed to support the depletion charge, and \(V_{FB}\) is the flat-band voltage, which depends on the work-function difference between gate and semiconductor and on fixed charges in the oxide. Factors affecting V_T: substrate doping (higher N_A gives higher V_T), oxide thickness (thinner oxide, larger C_ox, lower V_T), gate material (work function), oxide charges, temperature (V_T falls as temperature rises) and substrate bias (reverse body bias raises V_T, the body effect). Manufacturers adjust V_T by ion implantation of the channel region. Typical V_T values are about 0.3 to 0.7 V in modern logic and 1 to 4 V in discrete power MOSFETs.

MOSFET applications and MOSFET as a switch: The MOSFET is the most manufactured device in history. As a switch: with V_GS below V_T the channel is absent, I_D ≈ 0 and the switch is OFF (open, very high resistance). With V_GS well above V_T (for example 10 V for a power MOSFET or the logic supply in ICs), the device is in the ohmic region with a small on-resistance \(R_{DS(on)}\) (milliohms to ohms), so it acts as a closed switch, and the power loss is \(I_D^2R_{DS(on)}\). Because the gate draws no steady current, a microcontroller pin can drive it directly (logic-level MOSFETs), and the switching is fast because there is no minority carrier storage. In digital circuits, a p-channel and an n-channel E-MOSFET connected in series form the CMOS inverter: when the input is high the nMOS is ON and the pMOS OFF, so the output is pulled low; when the input is low the pMOS is ON and the nMOS OFF, so the output is high. In either steady state one transistor is off, so almost no static current flows; this is why CMOS logic uses very little power and is used in all processors and memories. Other applications: power MOSFETs in switch-mode power supplies, DC-DC converters, motor drivers, inverters, battery chargers and electric vehicles; analog switches and multiplexers; amplifiers (with high input impedance, as in the front ends of instruments); memory cells (DRAM uses one MOSFET and a capacitor; flash memory uses floating-gate MOSFETs); voltage-controlled resistors; and sensors (ISFETs for pH, MOS gas sensors).

Mind map

Formation of the channel in an n-channel E-MOSFET

Important definitions

Formulas

Key points to remember

• FETs are unipolar and voltage controlled; BJTs are bipolar and current controlled.
• JFET gate junction is always reverse biased; JFET is a depletion-mode (normally ON) device.
• At VGS = VP the JFET channel is closed; at VGS = 0 the saturated current is IDSS.
• MOSFET gate is insulated by SiO2, so the input resistance is extremely high.
• E-MOSFET: normally OFF; conducts only for VGS > VT (n-channel). Symbol has a broken channel line.
• D-MOSFET: normally ON; works in both depletion (VGS < 0) and enhancement (VGS > 0) modes.
• Saturation begins at VDS = VGS − VT (E-MOSFET) or VDS = VGS − VP (JFET).
• VT rises with substrate doping and oxide thickness and falls with temperature.
• MOSFET switch: OFF below VT; ON with low RDS(on); no gate current in steady state.
• CMOS draws almost no static power because one transistor of each pair is always OFF.
• Handle MOSFETs carefully: static charge can puncture the thin gate oxide.

Solved examples

Example 1. A JFET has IDSS = 10 mA and VP = −4 V. Find ID and gm at VGS = −2 V.

\(I_D = 10(1 - (-2)/(-4))^2 = 10(1 - 0.5)^2 = 2.5\) mA. \(g_{m0} = 2\times10/4 = 5\) mS; \(g_m = 5(1 - 0.5) = 2.5\) mS.

Example 2. For the same JFET, what VGS gives ID = 4 mA?

\((1 - V_{GS}/V_P)^2 = 4/10 = 0.4\), so \(1 - V_{GS}/V_P = \sqrt{0.4} = 0.632\). \(V_{GS}/V_P = 0.368\), \(V_{GS} = 0.368\times(-4) = -1.47\) V.

Example 3. An n-channel E-MOSFET has VT = 2 V and ID = 10 mA at VGS = 6 V (in saturation). Find k and ID at VGS = 4 V.

\(k = I_D/(V_{GS} - V_T)^2 = 10/(6 - 2)^2 = 0.625\) mA/V². At 4 V: \(I_D = 0.625\times(4 - 2)^2 = 2.5\) mA.

Example 4. A D-MOSFET has IDSS = 8 mA and VP = −3 V. Find ID at VGS = −1 V and at VGS = +1 V.

\(V_{GS} = -1\) V: \(I_D = 8(1 - 1/3)^2 = 8\times0.444 = 3.56\) mA (depletion mode). \(V_{GS} = +1\) V: \(I_D = 8(1 + 1/3)^2 = 8\times1.778 = 14.2\) mA (enhancement mode, above I_DSS).

Example 5. A power MOSFET with RDS(on) = 0.05 Ω switches a 5 A load. Find the conduction loss.

\(P = I^2R_{DS(on)} = 5^2\times0.05 = 1.25\) W. A BJT with V_CE(sat) = 0.3 V would lose 1.5 W plus base drive power, so low R_DS(on) MOSFETs are preferred for efficient switching.

Example 6. An n-channel MOSFET has tox = 10 nm, NA = 10^23 m^-3 and an assumed flat-band voltage VFB = −0.9 V (a typical value for an n⁺ polysilicon gate on p-type silicon, neglecting oxide charge; it is not calculated here). Find Cox, φF and VT at 300 K (ni = 1.5 × 10^16 m^-3, εs = 11.7ε0).

\(C_{ox} = 3.9\times8.85\times10^{-12}/10^{-8} = 3.45\times10^{-3}\) F/m². \(\phi_F = 0.02585\ln(10^{23}/1.5\times10^{16}) = 0.02585\times15.71 = 0.406\) V, so \(2\phi_F = 0.812\) V. Depletion charge \(Q_d = \sqrt{2\times11.7\times8.85\times10^{-12}\times1.6\times10^{-19}\times10^{23}\times0.812} = 1.64\times10^{-3}\) C/m²; \(Q_d/C_{ox} = 0.475\) V. \(V_T = -0.9 + 0.812 + 0.475 = 0.39\) V. This result depends on the assumed VFB. (With \(n_i = 1.0\times10^{16}\) m⁻³: \(2\phi_F = 0.833\) V, \(Q_d/C_{ox} = 0.482\) V and \(V_T = 0.41\) V.)

Important questions and answers

Q1. Explain the construction and working of an n-channel JFET with its characteristics. (6 marks)

Construction: n-type bar with source and drain contacts at the ends; two p⁺ gate regions on opposite sides connected together; channel between them. Working: V_DD makes the drain positive; V_GG reverse biases the gate. Electrons flow from source to drain through the channel; the reverse-biased gate junctions have depletion regions that extend into the channel, controlling its width. More negative V_GS means narrower channel and less current. Depletion is wider near the drain because the reverse bias is larger there; at pinch-off the current saturates. Drain characteristics: I_D vs V_DS for V_GS = 0, −1, −2, −3 V, showing ohmic region, pinch-off, saturation and breakdown. Transfer characteristic: parabola I_D = I_DSS(1 − V_GS/V_P)². Parameters: I_DSS, V_P, g_m, r_d.

Q2. Explain the construction and working of an n-channel enhancement MOSFET. (6 marks)

Construction: p substrate, n⁺ source and drain, thin SiO2 over the channel region, gate metal or polysilicon, contacts; substrate tied to source. Symbol with broken channel line and arrow on the substrate pointing in. Working: at V_GS = 0 no channel, I_D = 0. Positive V_GS repels holes and attracts electrons; at V_T an inversion layer forms and conducts. For V_GS > V_T, I_D increases with V_GS. With increasing V_DS, channel narrows at the drain end and pinches off at V_DS = V_GS − V_T; I_D saturates at k(V_GS − V_T)². Characteristics: drain curves for several V_GS values, with the parabolic boundary between ohmic and saturation regions; transfer curve starting at V_T.

Q3. Explain the depletion MOSFET and its two modes of operation. (5 marks)

Construction: like the E-MOSFET but with a lightly doped n channel diffused between source and drain. Symbol with solid channel line. Depletion mode: negative V_GS induces positive charge in the channel, repelling electrons and narrowing the effective channel; I_D falls below I_DSS and becomes zero at V_P. Enhancement mode: positive V_GS attracts additional electrons from the substrate into the channel; I_D rises above I_DSS. Since the gate is insulated, no gate current flows in either mode. Transfer characteristic: parabola through I_DSS at V_GS = 0, extending into both negative and positive V_GS.

Q4. Compare enhancement and depletion MOSFETs. (4 marks)

Channel: E-MOSFET has no physical channel (induced by gate); D-MOSFET has a built-in channel. At V_GS = 0: E-MOSFET OFF; D-MOSFET ON with I_DSS. Operation: E-MOSFET only enhancement (V_GS > V_T for n-channel); D-MOSFET both modes. Key parameter: V_T for E-type; I_DSS and V_P for D-type. Equation: k(V_GS − V_T)² versus I_DSS(1 − V_GS/V_P)². Symbol: broken versus solid channel line. Uses: E-MOSFETs in digital ICs, CMOS logic and power switching; D-MOSFETs in some RF amplifiers and as current sources and loads.

Q5. What is threshold voltage? On what factors does it depend? (5 marks)

V_T is the minimum gate-source voltage that produces strong inversion at the silicon surface (surface potential 2φ_F), forming a conducting channel in an E-MOSFET. Expression: \(V_T = V_{FB} + 2\phi_F + \sqrt{2\varepsilon_seN_A(2\phi_F)}/C_{ox}\). Terms: V_FB accounts for gate-semiconductor work function difference and oxide charges; 2φ_F is the band bending needed for inversion; the last term is the voltage across the oxide needed to hold the depletion charge. Dependence: higher substrate doping raises V_T; thicker oxide (smaller C_ox) raises V_T; gate material changes V_FB; positive oxide charges lower V_T of n-channel devices; higher temperature lowers V_T; reverse body bias raises V_T. It is adjusted by channel ion implantation.

Q6. Explain the MOSFET as a switch. (5 marks)

Circuit: n-channel E-MOSFET with load R_D from V_DD to drain, source grounded, control voltage at the gate. Input low (V_GS < V_T): no channel, I_D ≈ 0, V_out = V_DD: switch OFF. Input high (V_GS ≫ V_T): device in ohmic region with small R_DS(on), V_out ≈ I_DR_DS(on) ≈ 0, load gets nearly V_DD: switch ON. Advantages: zero steady gate current, fast switching (majority carriers only, no storage time), low on-resistance, easy paralleling, no thermal runaway. CMOS inverter: pMOS from V_DD to output, nMOS from output to ground, gates tied together; input high turns nMOS ON and pMOS OFF (output low) and vice versa; negligible static power. Applications: SMPS, motor and LED drivers, battery protection, load switches, digital logic.

Q7. Compare FET and BJT. (4 marks)

FET: unipolar, voltage controlled, very high input impedance, low noise, no offset voltage when used as a switch, good thermal stability, smaller and easier to integrate, lower gain-bandwidth in some cases, square-law transfer. BJT: bipolar, current controlled, low to moderate input impedance, higher transconductance at the same current, more noise, thermal runaway possible, exponential transfer, larger in ICs.

Exam tips

• Draw cross-sections with labelled source, drain, gate, oxide, substrate, channel and depletion regions.
• Learn the symbols of n- and p-channel JFET, E-MOSFET and D-MOSFET; broken line = enhancement.
• Do not mix the equations: Shockley for JFET and D-MOSFET, k(V_GS − V_T)² for E-MOSFET.
• Keep signs: for n-channel JFET, V_P and V_GS are negative, so V_GS/V_P is positive.
• In switch questions mention R_DS(on) and the zero gate current.

FAQs

Why is the MOSFET called an insulated gate FET?

Its gate is separated from the channel by a thin insulating oxide layer, so no DC current flows into the gate.

Why must a JFET gate not be forward biased?

Forward biasing the gate junction makes it conduct like a diode, destroying the high input impedance and possibly damaging the device. A D-MOSFET can take positive gate voltage because its gate is insulated.

What does the arrow on the MOSFET symbol show?

It marks the substrate (body) and points from p to n: inwards for n-channel devices (p substrate) and outwards for p-channel devices.

Why are MOSFETs damaged by static electricity?

The gate oxide is only nanometres thick, and a static charge of a few hundred volts creates a field large enough to break it down permanently. Handle them on grounded mats and keep their leads shorted until use.

These notes follow the University of Mumbai first-year engineering syllabus (NEP 2020, Semiconductor Physics, Semester II) and were prepared with AI help and checked.